Half adder and Full adder
AIM:
To construct and verify the operation of Half adder and Full adder using logic gates.
APPARATUS REQUIRED:
| S.NO | COMPONENTS | RANGE | QUANTITY |
| 1 | Digital Trainer Kit | | 1 |
| 2 | IC 7486 | | 1 |
| 3 | IC 7408 | | 1 |
| 4 | IC 7432 | | 1 |
| 5 | Connecting wires | | As required |
CIRCUIT DIAGRAM:
Half Adder:
Full Adder:
TRUTH TABLE:
Half Adder
| X | Y | S | C |
| 0 0 1 1 | 0 1 0 1 | 0 1 1 0 | 0 0 0 1 |
Full Adder
| X | Y | Z | S | C |
| 0 0 0 0 1 1 1 1 | 0 0 1 1 0 0 1 1 | 0 1 0 1 0 1 0 1 | 0 1 1 0 1 0 0 1 | 0 0 0 1 0 1 1 1 |
PROCEDURE:
1. Circuit connections are given as per the circuit diagram.
2. The +5V DC power supply is properly connected to Vcc and GND pins
(14 & 7) of each IC.
3. Logical input conditions are given as per the Truth Table.
4 .Logical outputs are observed and verified.
RESULT:
Thus the Half Adder and Full Adder circuit is constructed and the output is verified using the Truth Table.
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ENCODER AND DECODER
AIM:
To construct and verify the operation of Encoder and Decoder using logic gates.
APPARATUS REQUIRED:
| S.NO | COMPONENTS | RANGE | QUANTITY |
| 1 | Digital Trainer Kit | | 1 |
| 2 | IC 7404 | | 1 |
| 3 | IC 7408 | | 1 |
| 4 | IC 7432 | | 1 |
| 5 | Connecting wires | | As required |
CIRCUIT DIAGRAM:
3-to-8 line DECODER
Octal to Binary ENCODER
Expression:
PROCEDURE:
1. Circuit connections are given as per the circuit diagram.
2. The +5V DC power supply is properly connected to Vcc and GND
pins(14 & 7) of each IC.
3. Logical input conditions are given as per the Truth Table.
4. Logical outputs are observed and verified.
RESULT:
Thus the Encoder and Decoder circuit is constructed and the output is verified using the truth Table.
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